1. Field of the Invention
The invention relates to a new organization of memory for a data processing system.
2. Description of the Prior Art
In the present specification, the term "shift-register" will generally be used for indicating a block-shifting register; also, the term "read-write means" associated with a "shift-register" will indicate a block read-write means. In the prior art, the access time for a shift-register is equal to L/2, L being the length of the shift-register. In U.S. Pat. No. 3,735,361, a memory organization for obtaining an average access time in the range of only one or few steps of a shift-register is disclosed. This organization may replace the random main memory and possibly the "cache". Accordingly, the relative independence of the average access time with respect to the length of the shift-register enables utilization of sets of shift-registers having a great length as main memories and accordingly to substantially reduce the bit cost and the bulk of main memories. According to U.S. Pat. No. 3,735,361 which will be incorporated herein by reference, each large shift-register comprises at least one read-write means and constitutes a memory section. Accordingly, if N sections are used, N blocks are accessible without shifting. Accordingly, in each section, the cited patent provides for the arrangement of blocks into "pages" of at least one block and it appears from experiments that in a given page comprising adjacent blocks of the main memory, there is a large probability that successive requests from the computer processor relate to the same page or the same block (refer to J. Tasso, Memoires sequentielles d'apparence aleatoire utilisables comme memoires centrales-- Communication 64 pages 330-341, International symposium on Memories-- Paris Oct. 23-26, 1973, published by Societe des Electriciens, Electroniciens et Radioelectriciens).
There is also a large probability that the read-write means of each memory section looks successively for data in the same page, in particular in a shift-register forming a section (a section shift-register). Accordingly, for embodying the memory organization disclosed in the referred to patent, it is necessary to have the possibility to stop actually or ficticiously a given block in front of the read-write device of the associate section, that is the shift-register has to be static or pseudo-static. The pseudo-static shift-registers comprise the dynamic registers in which to-and-fro refreshment local oscillations are provided.
Ideal shift-registers for implementing the memory organization described in the cited patent would be high-speed, static or pseudo-static two-way shift-registers having a low bit cost. In fact, it appears that the shift-registers having the lowest bit cost have not, or have only partially, the three other features. For example, the charge coupled device (CCD) registers are not static and necessitate a refreshment; the magnetic bubble shift-registers are static but relatively slow; the magnetic disks or drums which are in permanent rotation can simulate shift-registers but are not static. It should be noted that, when using magnetic disks, drums or tapes, a serial/parallel conversion would be preferably made in order to form block registers and to form the various sections of the registers; otherwise a too great disk number would be necessary. On the other hand, static and two-way shift-registers such as for example static or pseudo-static flip-flop registers have a bit cost which is presently relatively expensive.